The present invention relates to optimizing the layout of conductive lines in an integrated circuit (IC) chip. More particularly, the present invention relates to algorithms for optimizing layout of conductive lines to minimize the occurrence of sensitive areas that are susceptible to defects from particles.
During IC fabrication, the IC is exposed to a number of particles or particle defects, which may come from workers in the fabrication facility, equipment or processing chemicals employed during the fabrication process, etc. The particles typically range from about 0.1 micrometers (.mu.m) to about 10 micrometers (.mu.m) in size. With each new generation of ICs, the device feature size decreases, thereby increasing the susceptibility of the IC to defects from still smaller particles. While improvements in clean room technology reduce the average particle size in critical fabrication facilities, some damaging particles always can be expected to be present. Today's ICs, which include semiconductor devices that have feature sizes of about 0.3 .mu.m, for example, are vulnerable to submicron sized particles. Such particles can short the closely spaced conductive lines in the IC circuitry due to today's small line widths and line separations.
FIG. 1A shows an idealized simple layout of a conventional IC design 10 that includes logic cells and conductive lines. A region of interest 11 has a conductive line 12, which provides an input signal "A" to cells 16 and 18 that generate output signals "C" and "D," which are transmitted through conductive lines 22 and 24, respectively. Similarly, region 11 includes another conductive line 14, which provides another input signal "B" to cell 20 that generates an output signal "E," which is transmitted through conductive line 26. These conductive lines typically include polysilicon or a metal. It should be understood that in actual designs, some or all elements of the logic cells may exist at layers other than the layer on which the conductive lines exist.
In many conventional wiring layout tools, the routing of conductive line 26 is always chosen to minimize delay, unless timing requires that a particular signal be slightly delayed. This overriding focus on minimizing delay (and shortening wire length) can inadvertently create regions susceptible to particle defects. Conductive line 26, as shown in FIG. 1A, is close enough to conductive line 24 to form an area that is sensitive to a particle, i.e. a particle 28, which is present in this area and in physical contact with conductive lines 26 and 24 may short-circuit output signals D and E. Such an area is hereinafter referred to as a "sensitive area." If conductive lines 26 and/or 24 represent a critical path, particle 28 is likely to render the entire design 10 inoperable and may be referred to as a "killer defect."
Particle 28, shown in FIG. 1A, may be introduced into the IC during the various stages of IC fabrication. By way of example, particle 28 may be introduced before or after the conductive lines have been formed. Before the conductive lines are formed, for example, a particle present on a blanket deposited photoresist layer, which overlies the metallization layer, prevents a part of the photoresist layer that is underlying the particle from being exposed to a light source. As a result, before the metallization layer is etched to form conductive lines, a photoresist mask is not developed in that part of the photoresist layer and that part of the metallization layer remains unetched. Unfortunately, the unetched part of the metallization may undesirably connects two conductive lines rendering the IC inoperable. One skilled in the art may also appreciate that such particles also pose a risk of creating a short-circuit between two conductive lines at different levels of metallization.
FIG. 1B shows a more detailed view of conductive lines having sensitive areas in a layout scheme of another conventional IC design 50. Sensitive areas 52, 54 56 and 58, for example, are manifested as sharp corners of conductive lines that are positioned close to adjacent conductive lines, as shown. The presence of a particle in these sensitive areas would be detrimental to the IC performance as described above.
The layout design of IC devices, such as metal oxide semiconductor (MOS) transistors, and circuits is constrained by a set of rules called the "design rules." These rules are technology specific and specify minimum sizes, spaces and overlaps for the various features (e.g. lines) that define the IC device. Processes are designed around a minimum feature size, which is the width of the smallest line or space that can be reliably transferred to the surface of the wafer using a given generation of lithography.
While design rules for automatic placement of conductive lines provide a minimum separation distance, they do not account for the general need to arrange the conductive lines in such a manner so that the sensitive areas are minimized. The design rules that dictate the conventional IC layout, are guided only by the criteria of minimizing overall chip size and maximizing performance. By way of example, these criteria may be accomplished by making sure that a conductive line does not take a circuitous path or takes the shortest distance between two contact points, e.g., cells or logic gates. Unfortunately, because conventional design criteria do not account for the sensitive areas, IC yield is unduly low.
What is needed is a method that optimizes a layout of conductive lines in an integrated circuit (IC) chip, such that sensitive areas that are susceptible to defects are minimized without increasing the overall size of the IC or detrimentally affecting the performance of the IC design.